1. Field of Invention
This invention relates generally to content addressable memories and specifically to a Multi-Chip-Module (MCM) system for content addressable memory.
2. Description of Related Art
A content addressable memory (CAM) device is a storage device having an array of memory cells that can be instructed to compare the specific pattern of comparand data with data words stored in corresponding rows of the array. The entire CAM array, or segments thereof, are searched in parallel for a match with the comparand data. If a match exists, the CAM device indicates the match condition by asserting a match flag, and may indicate the existence of multiple matches by asserting a multiple match flag. The CAM device typically includes a priority encoder that provides the highest priority matching address (e.g., the lowest matching CAM index) to a status register. The highest priority matching address, the contents of the matched location, and other status information (e.g., skip bit, empty bit, full flag, as well as match and multiple match flags) may be output from the CAM device to an output bus. In addition, associative data may be read out from an associated addressable storage device (e.g., DRAM).
Due to the rapidly increasing number of addressable sites on the Internet, there is an ongoing desire to increase the storage capacity of CAM devices used for Internet routing applications. This ongoing desire fuels development of future generations of CAM devices that have more storage capacity than previous generations. Each new generation of CAM devices typically has about twice the storage density as previous generation CAM devices.
The ability to be the first to market in offering a next generation CAM device having twice the storage capacity of current generation CAM devices provides a distinct competitive advantage. However, implementing a CAM device in a new process technology to double the storage density requires considerable time and expense, and may be dependent upon others (e.g., wafer manufacturers) to perfect the new process technology. Alternately, creating a new array architecture having twice the storage capacity using current process technology may require considerable time and expense to develop, and may occupy as much as twice the area of the silicon wafer. As a result, the number of manufacturing defects on the wafer that affect the CAM array increases, thereby decreasing manufacturing yield. Further, the increased size of the CAM array may result in the CAM die exceeding present photolithographic stepping dimensions, e.g., the photolithographic stepping fields may be smaller than the individual dice, in which case fabrication using present process technology may not be possible.
Thus, it is desirable to increase the storage capacity of CAM devices without having to develop a new process technology or CAM array architecture.
A method and apparatus are disclosed that allow for the storage capacity of a CAM device to be significantly increased more easily and more quickly as compared to the prior art. In accordance with the present invention, a monolithic Multi-chip Module (MCM) package includes two or more individual CAM dice mounted on a substrate and encapsulated in, for example, a plastic ball grid array (PBGA) package. The substrate includes an interconnect structure to route signals between corresponding pads of the CAM dice and balls of the MCM package.
For one embodiment, the footprint of the MCM ball grid array package including multiple CAM dice is identical to the footprint of a ball grid array package including a single CAM die. By including a plurality of CAM dice within an MCM package that has the same footprint as a package housing a single CAM die, customers may significantly increase storage capacity by simply replacing the individual CAM die package with an MCM package in accordance with the present invention. Because the footprints are the same, the MCM package may utilize the same socket previously used by the individual die package without altering the system layout or design. Further, because MCM packages of the present invention may be fabricated using current process technologies and proven CAM array architectures, the commercial availability of such MCM packages is not dependent upon development of a next generation process technology or a larger CAM array architecture. As a result, MCM packages in accordance with the present invention may be fabricated and made available to customers long before the next generation CAM device, as traditionally defined, is developed. The ability of present embodiments to provide customers with a monolithic CAM package having significantly increased storage capacity long before others may translate into a significant competitive advantage.
For some embodiments, each CAM die housed within the MCM package is assigned the same device identification number (DID) so that the MCM package has only one associated DID, as may be preferred by customers. For these embodiments, the MCM package utilizes a transparent cascade technique in accordance with the present invention to depth cascade the CAM dice in such a way that the MCM package appears and effectively operates as a single CAM device.
Each CAM die may include additional pads to receive a select signal, a mode signal, and a priority address bit. The select signal is used to simultaneously write the same DID into all CAM dice housed in the MCM package. The mode signal indicates, in one state, that the CAM die is configured to operate in a depth cascade configuration with one or more other CAM dice that each have the same DID and, in another state, that CAM die is configured to operate as a single device or in a depth cascade configuration with one or more other CAM devices that each have different DIDs. The priority address bit is used to assign priority between the CAM dice within the MCM package. The mode and priority address signals may be multiple-bit signals. In one embodiment, the select, mode, and priority address signals are provided internally within the MCM package, and are thus transparent to users or systems employing the MCM package.
Each CAM die may include a status register that stores the priority address bit, the DID, and highest-priority matching (HPM) index, and one or more flag signals. The priority address bit associated with each CAM die indicates the most significant address bit for the address space formed by the cascaded CAM dice. The priority address bit may be considered as the most significant bit (MSB) of the HPM index or, alternately, as the least significant bit (LSB) of the DID. During compare operations, the priority address bit is inserted between the DID and HPM index to form the device index. During read and write operations, the priority address bit is used to select one of CAM die within the MCM package for the operation.